Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “lens”; however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens”. Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). As is known, optical proximity correction (OPC) features may be incorporated into the mask design to enhance the resulting image such that it more accurately represents the target pattern. Further, it is also known to utilize models of the desired process to simulate the aerial image of a given target pattern. Such models allow the operator to review the effects of adjusting masking features and OPC features on the resulting image without having to actually image a wafer, thereby saving both significant cost and time in the design process. One such modeling method is described in U.S. application Ser. No. 10/981,750, filed on Nov. 5, 2004, which is hereby incorporated by reference in its entirety.
Another goal in photolithography is to be able to utilize the same “process” for imaging a given pattern with different lithography systems (e.g., scanners) without having to expend considerable amounts of time and resources determining the necessary settings of each lithography system to achieve optimal/acceptable imaging performance. As is known, designers/engineers spend a considerable amount of time and money determining the optimal settings of a lithography system, which include numerical aperture (NA), σin, σout, etc., when initially setting up a given process to work with a particular scanner so that the resulting image satisfies the design requirements and process robustness requirements. Indeed, finding an optimal photolithography process condition for each layer involves enormous effort from the engineering side through simulations and experiments. A method for allowing a given process to be utilized with different lithography systems is disclosed in U.S. patent application Ser. No. 10/926,400 filed on Aug. 26, 2004, which is hereby incorporated by reference herein in its entirety.
As noted above, target patterns are typically subjected to a simulation process using a calibrated model of the photolithography process so as to allow the designer to optimize the mask pattern such that the resulting image matches the target pattern within a defined tolerance. The model used in such data manipulation, which is commonly referred as to model OPC, is typically calibrated on a specific exposure tool under specific exposure conditions. However, as noted above, it is not uncommon for a photolithography process to be exported onto other exposure tools of the same class, in order to satisfy the high volume production requirements in a manufacturing environment. As such, it is highly desirable to be able to utilize the model calibrated on a first exposure tool on another exposure tool, without having to perform another complete calibration process, which is both expensive and time consuming. Currently, there is no known method for allowing a model calibrated on a first exposure tool to be utilized with another exposure tool without performing a complete calibration process on the other exposure tool.